library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fsmd_counter is
port(clk,reset:in std_logic;
	counter:out unsigned(2 downto 0);
	full:out std_logic);
end entity fsmd_counter;
architecture fsmd_arch of fsmd_counter is
type state is (idle,op,done); 
signal state_ps, state_ns: state;  
signal cnt_ps, cnt_ns: unsigned(2 downto 0);  
signal number_ps, number_ns: unsigned(2 downto 0);
 begin --fsmd state and data registers 
 p1:process(clk,reset) 
 begin  
 if reset='1' then  
 state_ps<=idle;  
 cnt_ps<=(others=>'0');  
 number_ps<=(others=>'1');  
 elsif (clk'event and clk='1') then  
 state_ps<=state_ns;  
 cnt_ps<=cnt_ns;  
 number_ps<=number_ns;  
 end if; 
 end process p1; 
 --fsmd next—state logic 
 p2:process(state_ps,cnt_ps,number_ps) 
 begin  case state_ps is  
 when idle=>  
 full<='0';  
 cnt_ns<=(others=>'0');  
 number_ns<=(others=>'1');  
 state_ns<=op;  
 when op=>  
 if number_ps="000" then  
 full<='0';  
 state_ns<=done;  
 else  
 full<='0';  
 state_ns<=op;  
 cnt_ns<=cnt_ps+1;  
 number_ns<=number_ps-1;  
 end if;  when done=>  
 full<='1';  
 state_ns<=idle;  
 end case; 
 end process; 
 --output  
 counter<=cnt_ps; 
 end architecture fsmd_arch; 